1. Field of the Invention
The present invention relates to an ion implanter and a method of manufacturing a semiconductor device including an ion implanting process.
2. Description of the Related Art
In recent years, large scale integrated circuits (LSI) have often been used in important parts of computers and communication apparatuses; the large scale integrated circuits are formed by connecting a large number of transistors and resistors together as electric circuits and integrating the circuits together on one chip. Thus, the performance of the whole apparatus depends strongly on the performance of a single LSI. The performance of the single LSI can be improved by increasing the degree of integration, that is, miniaturizing the elements.
Miniaturization of elements can be formed by reducing the junction depth of a diffusion layer, for example, a source/drain diffusion layer. The junction depth can be reduced by optimizing ion implantation and the subsequent heat treatment step (annealing). This serves to realize, for example, a MOS transistor having a shallow source/drain diffusion layer of junction depth not higher than 0.2 μm.
To form a shallow diffusion layer by doping impurities, it is necessary to make a reduced heat budget so as to shallowly distribute impurity atoms during ion implantation and to prevent the impurity atoms from diffusing deeply during the subsequent heat treatment. Further, to use impurity doping to form wells in which elements such as MOS transistors are formed and areas (channel doping layers) in which channels of MOS transistors are induced, it is necessary to accurately control the amount of impurities implanted.
On the other hand, with a miniaturization of elements, for example, a reduction in gate processing size, offset is more likely to occur in a source/drain area owing to shadowing of a gate electrode and deviation of the incident angle of ion beam. Such offset makes notable transistor characteristics asymmetric.
A cone angle has been considered to be the cause of the asymmetry of the transistor characteristics which may occur if a batch type high current ion implanter is used. Thus, attempts have been made to eliminate the asymmetry of the transistor characteristics by adjusting an α angle and a β angle (Extended Abstracts of International Workshop on Junction Technology 2002, S2-3.).
However, at present, the asymmetry of the transistor characteristics is not necessarily eliminated simply by adjusting the α and β angles.